This relates generally to integrated circuits, and more particularly, to integrated circuits with memory.
Integrated circuits with memory are often used to support high speed data transfer between different network components. In particular, such types of integrated circuits typically include random access memory (RAM) elements arranged in an array. Consider a scenario in which an integrated circuit receives bursts of eight data words at regular time intervals. Each burst of eight data words can then be stored in a selected row in the RAM array.
In the scenario above, it may sometimes be desirable to retrieve a group of eight data words that span a portion of a first row in the RAM array and a portion of a second row that is adjacent to the first row. In conventional memory addressing schemes, data can only be read out on a row-by-row basis. In order to retrieve the group of eight data word spanning the two rows, the entire first and second rows will have to be read out. Since each of the first and second rows includes eight data words, a total of 16 data words will have to be read out. The desired group of eight data words can then be extracted from the 16 data words that have been read out.
In modern high speed data communications network, handling data using this conventional approach can be unacceptably inefficient. It may therefore be desirable to provide interface circuitry with improved memory addressing capabilities.